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this is information on a product in full production. may 2012 doc id 17588 rev 4 1/20 20 SPV1020 interleaved dc-dc boost converter with built-in mppt algorithm datasheet ? production data features pwm mode dc-dc boost converter duty cycle controlled by mppt algorithm with 0.2% accuracy operating voltage range 6.5 - 40 v overvoltage, overcurrent, overtemperature protection interleaved 4-phase topology built-in soft-start up to 98% efficiency power capability 320 w at 40 v output automatic transition to burst mode for improved efficiency at low solar radiation spi interface applications photovoltaic panels battery charging with a cvcc controller description the SPV1020 is a monolithic 4-phase interleaved dc-dc boost converter designed to maximize the power generated by photovoltaic panels independent of temperature and amount of solar radiation. optimization of the power conversion is obtained with embedded logic which performs the mppt (max. power point tracking) algorithm on the pv cells connected to the converter. one or more converters can be housed in the connection box of the pv panels, replacing the bypass diodes. as the maximum power point is locally computed, the efficiency at system level is higher than that of conventional topologies, where the mpp is computed in the main centralized inverter. for a cost effective application solution and to minimize size, the SPV1020 embeds power mosfets for active switches and synchronous rectifiers, minimizing the number of external devices. in addition, the 4-phase interleaved topology of the dc-dc converter obviates the need to use electrolytic capacitors, which may severely limit system lifetime. the SPV1020 operates at fixed frequency in pwm mode, where the duty cycle is controlled by the embedded logic running a perturb&observe mppt algorithm. the switching frequency, internally generated and set by default at 100 khz, is externally adjustable from 50 khz to 200 khz, while the duty cycle can range from 5% to 90% with a step of 0.2%. the safety of the application is guaranteed by stopping the drivers in the case of output overvoltage or overtemperature. multiple SPV1020s can be used in a panel array with one SPV1020 per panel. panels can be connected in series, in parallel, or series/parallel combinations. table 1. device summary order codes package packaging SPV1020 powersso-36 tube powersso-36 www.st.com
contents SPV1020 2/20 doc id 17588 rev 4 contents 1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 initialization and startup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 input voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 output voltage sensing and overvoltage protection (ovp) . . . . . . . . . . . . 10 5.5 overcurrent protection (ocp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 overtemperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.7 shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.9 mppt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.10 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.11 spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPV1020 application circuit doc id 17588 rev 4 3/20 1 application circuit figure 1. application circuit 9287 &% /; 3*1' 9287 9287b616 26&b,1 3=b287 9287 &% /; 3*1' /; &% 9287 9,1 9,1b616 9,1b616b0,186 ;& 6 63,b '$7$b,1 63,b'$7$b287 6*1' 63,b& /. /; &% 95(* 3*1' 9287 3*1' / / / / & & & & 5 5 5 & 5 & 5 & & & 9lq 3lq 3lq ' ' 39&hoov ' 9lq 9287 & &
pin connection SPV1020 4/20 doc id 17588 rev 4 2 pin connection figure 2. pin connection (top view) 6/54 6/54 #" ,8 ,8 0'.$ 0'.$ ,8 ,8 #" 6/54 6/54 8#3 30)?$!4!?). 30)?#,+ 6). 6).?3.3 6).?3.3?- 6/54 6/54 #" ,8 ,8 0'.$ 0'.$ ,8 ,8 #" 6/54 6/54 30)?$!4!?/54 62%' /3#?). 6/54?3.3 0:?/54 3'.$
SPV1020 pin connection doc id 17588 rev 4 5/20 table 2. pin description pin name type description powersso-36 34 vin supply dc input power supply unit. 7,8,17,18,19,20,29,30 vout supply booster output voltage 12,13,24,25 pgnd ground power ground 1sgndground signal ground reference. the exposed pad is connected to pgnd. 22,23,26,27,15,14,11,1 0 lx1?4 i booster inductor connection. 9,16,21,28 cb1?4 i/o external bootstrap capacitors must be connected between these pins and lxi 5 vreg i/o power supply for internal low voltage circuitry; an external capacitor must be connected to this pin referenced to sgnd 35 vin_sns i sense pin of input voltage. to be biased with a resistor divider between vin and sgnd 3vout_snsi sense pin of output voltage. to be biased with a resistor divider between vout and sgnd 31 xcs i activates the spi 36 vin_sns_m i dedicated ground for vin_sns 2 pz_out i/o compensates the output voltage feedback loop. a series resistor and capacitor are connected between pz_out and sgnd. 6 spi_data_out o data out for spi interface 33 spi_clk i clock for spi interface. 32 spi_data_in i data in for spi interface. 4osc_ini pin for adjusting the switching frequency; to set the default value of 100 khz, connect osc_in to vreg. otherwise connect osc_in through a resistor to sgnd.
maximum ratings SPV1020 6/20 doc id 17588 rev 4 3 maximum ratings 3.1 absolute maximum ratings table 3. absolute maximum ratings symbol parameter range [min., max.] unit vin power supply [-0.3, 40] v vout power supply [-0.3, 40] v pgnd power ground 0 v sgnd signal ground [-0.3, 0.3] v vout_sns analog input [-0.3, vout + 0.3] v lx1?.4 analog input [-0.3, vout + 0.3] v cb1?4 analog input/output [lxi ? 0.3, lxi + 5] v vreg analog input/output [-0.3, 6] v vin_sns analog input [-0.3, 3.3 + 0.3] v xcs analog input [-0.3, 3.3 + 0.3] v osc_in analog input [-0.3, 3.3 + 0.3] v pz_out analog input/output [-0.3, vin + 0.3] v spi_data_out analog output [-0.3, 3.3 + 0.3] v spi_clk digital input [-0.3, 3.3 + 0.3] v spi_data_in digital input [-0.3, 3.3 + 0.3] v vin_sns_m dedicated ground [-0.3, 0.3] v table 4. thermal data symbol parameter min. typ. max. unit r thja (1) 1. r thja was measured with a 4-layer pcb, fr4 70 um cu thickness exposed pad soldered area = 30 mm2 thermal resistance, junction to ambient - 24 c/w tj op junction temperature operating range -40 - 125 c tstg storage temperature -50 - 125
SPV1020 electrical characteristics doc id 17588 rev 4 7/20 4 electrical characteristics v in = 36 v, t a = 25 c and t j <125 c, unless otherwise specified. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit input source section v in operating input voltage 6.5 40 v i q quiescent current iload=0 ma, vout=36 v, tj=tamb, pwm=5% 5ma i sd shutdown mode current consumption iload=0 ma, vout=vin=36 v, t j = ta m b 1ma v uvlo undervoltage lockout threshold for turn-on vin increasing 6.5 v undervoltage lockout hysteresis -0.5 v power section r dson-ls power switch on-resistance 70 m ? r dson-hs synchronous rectifier on-resistance 70 m ? control section v out operating output voltage vin 40 v i out operating output current 9 a i lim lx switch current limit 4 4.5 5 a f pwm pwm frequency (default value) 70 100 150 khz v ref constant voltage control loop internal reference voltage 1.18 1.23 1.27 v thermal shutdown t shutdown overtemperature threshold for turn-off temperature increasing 140 150 160 c overtemperature hysteresis -20 c
detailed description SPV1020 8/20 doc id 17588 rev 4 5 detailed description the SPV1020 is a fully integrated high efficiency dc-dc boost converter with 4-phase interleaved topology operating in the voltage range from 6.5 vdc to 40 vdc. a simplified block diagram showing only one of the four phases is shown in figure 3 below. figure 3. simplified block diagram 5.1 initialization and startup mode in order to guarantee a correct power-up sequence, the converter initially operates in burst mode. when the input voltage is greater than 6.5 v, the converter sequentially activates each of the four phases. initially, only phase 1 starts to work in burst mode, charging the inductor only for one cycle over 15 cycles. then the duty cycle is progressively increased until phase 1 is switched on at every cycle and at the default switching frequency of 100 khz. after phase 1 has reached its steady-state condition, all the other phases are progressively switched on in the following sequence: phase 3, phase 2 and, lastly, phase 4. all the sequences are running when the power generated by the pv cells is increasing. otherwise the sequence may go back and then forward again. 03 37 &w u o $' fr qy h uw hu $' fr qy h uw hu $ ' fr q yh uw h u 39fhoo vwulqj )dxow &w u o 9 p9 928 7 9287 b 616 /; 9, 1 b 61 6 3*1 ' 3*1 ' 9 3= b 28 7 9, 1 9% 95(* 2vf &% 9,1 ;& 6 6*1 ' 26& , 1 9,1b616b0 63, '$ 7$ ,1 63,b&/. 63,b'$7$b287
SPV1020 detailed description doc id 17588 rev 4 9/20 5.2 oscillator the switching frequency fswitch is internally fixed at 100 khz and each phase operates at the frequency fixed by the oscillator. to set the default value of 100 khz, connect osc_in to vreg. the switching frequency can be adjusted from 50 khz to 200 khz by connecting an external resistor r6 between osc and sgnd. the relationship between r6 and fswitch is: 5.3 input voltage sensing the device monitors the input voltage generated by the pv cells through vin_sns. this value is used to calculate the power generated by the pv cell string and then to adjust the pwm duty cycle to provide the maximum power point. the input voltage must be scaled to a reference voltage level of 1.25 v at the input of the adc integrated in the SPV1020. referring to the schematic shown in the application circuit of figure 1 , r1 and r2 are the resistors used for partitioning the input voltage. if vin_max is the maximum input voltage of the supply source (e.g. the pv panel or the pv string), r1 and r2 must be selected according to the following formula: equation 1 also, in order to optimize the efficiency of the whole system, when selecting r1 and r2, their power dissipation must be taken into account. assuming negligible the current flowing through pin vin_sns, maximum power dissipation in the series r1+r2 is: equation 2 as an empirical rule, r1 and r2 should be selected according to: equation 3 note: in order to guarantee the proper functionality of pin vin_sns, current flowing in the series r1+r2 should be in the range between 20 a and 200 a. r1 r2 ------- - v inmax 1.25 ----------------- - 1 ? = p vin_sns v in_max () r1 r2 + ------------------------ 2 = p vin_sns 0.1x v in_max i in_max ? () ?
detailed description SPV1020 10/20 doc id 17588 rev 4 5.4 output voltage sensing and overvoltage protection (ovp) another monitoring is carried out on vout with the vout_sns pin. this pin is used to monitor the output voltage in order to regulate it?s maximum value (which cannot exceed 40 v), preventing damage due to overvoltage. vout_sns (the partitioned vout) is checked against a threshold of 1.0 v, generated by an internal regulated voltage. when vout_sns reaches 1 v, the output feedback loop begins to regulate and limits the output voltage. the stability of the loop can be externally regulated by connecting a resistor and a capacitor (pole-zero compensation) between the pz_out and sgnd. if vout_sns exceeds 1.04 v a fault signal is generated and transmitted to the fault controller. this stops the drivers and produces a fault signal to an external chip (diag = 0). when vout_sns decreases down to 1.04 v, the boost converter begins to regulate again and the mppt restarts from the minimum duty cycle of 5%. referring to the schematic shown in figure 1 , r3 and r4 are the two resistors used to partition the output voltage. if vout_max is the maximum output voltage at the load, r3 and r4 must be selected according to the following rule: equation 4 also, in order to optimize the efficiency of the whole system, when selecting r3 and r4, their power dissipation must be taken into account. assuming negligible the current flowing through pin vout_sns, maximum power dissipation in the series r3+r4 is: equation 5 as an empirical rule, r3 and r4 should be selected according to: equation 6 note: in order to guarantee the proper functionality of pin v out_sns , current flowing in the series r3+r4 should be in the range between 20 a and 100 a. r3 r4 ------- - v outmax 1.02 -------------------- - 1 ? = p vout_sns v out_max () r1 r2 + --------------------------- - 2 = p vout_sns 0.1x v out_max i out_max ? () ?
SPV1020 detailed description doc id 17588 rev 4 11/20 5.5 overcurrent protection (ocp) to guarantee safe operation the low-side power switches have overcurrent protection. if lx is accidentally shorted to vin or vout or when the current flowing through the inductor exceeds the current limit (~4.5 a), the related low-side power switch is immediately turned off and the linked synchronous rectifier is turned on. the low-side power switch is turned on again at the next pwm cycle. 5.6 overtemperature protection (otp) when the temperature sensed at silicon level reaches 150 c, all low-side power switches are immediately turned off. the device becomes operative again as soon as the silicon temperature drops to 130 c. 5.7 shutdown in shutdown mode, the shut command sent to the converter switches the converter off to minimize power consumption. the synchronous rectifier intrinsic body diode causes a parasitic path between the power supply input and output, that cannot be avoided in shutdown. 5.8 undervoltage lockout (uvlo) when solar radiation is too low or the pv cells are shaded, the energy generated may be too small to drive the converter. in this case, when the input voltage is lower than the uvlo threshold, all circuitry is in the off state, avoiding undesired power consumption. hysteresis has been implemented to limit undesired switching of the internal reset circuits. 5.9 mppt in order to maximize the energy transferred from the pv cell string to the dc bus (connected to the output of the converter) the converter embeds a logic running a perturb&observe mppt algorithm based on monitoring the voltage and current supplied by the pv cells. if the operating voltage of the pv array is perturbed in a given direction and the power drawn from the pv array increases, this means that the operating point has moved towards the mpp and, therefore, the operating voltage must be further perturbed in the same direction. otherwise, if the power drawn from the pv array decreases, the operating point has moved away from the mpp and, therefore, the direction of the operating voltage perturbation must be reversed 5.10 spi the SPV1020 embeds a 4-pin compatible spi interface. the spi allows full duplex, synchronous, serial communication between a host controller (the master) and the SPV1020 peripheral device (the slave). the spi master provides the synchronizing clock and starts the communication. the idle state of the serial clock for the SPV1020 is high. data pins are driven on the falling edges of the serial clock and they are sampled on its rising edges. these features correspond to a clock polarity set to 1 (typical host spi control
detailed description SPV1020 12/20 doc id 17588 rev 4 bit cpol=1) and to a clock phase set to 1 (typical host spi control bit cpha=1), respectively. the bit order of each byte is msb first. when the master initiates a transmission, a data byte is shifted out through the mosi pin to the slave, while another data byte is shifted out through the miso pin to the master. the master controls the serial clock on the sclk pin. the ss (active low) pin must be driven low by the master during each transmission. the bit order of each byte is msb first. the SPV1020 register file is accessible by the host through the spi bus. therefore the host can read the SPV1020 control parameter register data. each data frame includes at least one command byte followed by data bytes whose direction depends on the type of command. if the command byte requires data to be read from the register file, those data are transmitted from the slave to the master through the miso pin. therefore the master appends a number of nops (0x00) to the command so that the entire data can be transmitted, see figure 4 . the master must transmit a byte to receive a byte. if the ss wire goes high before the completion of a command byte in the data frame, the SPV1020 rejects that byte and the frame is closed. then the next data frame is considered as a new one, starting with a command byte. figure 4. frame structure: register read operation the host can insert a short pause between each frame byte, or it can work in burst mode (no pause between frame bytes). some data words can be longer than 8 bits, such as adc results (10 bits). in such cases, data is first extended to the nearest multiple of one byte (right justified). then it is split into bytes, e.g. the adc result r is formatted as follows: table 6. data format for words longer than 8 bits bit 7msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb byte 10 00000 r9 msb r8 byte 2 r7 r6r5r4r3r2 r1 r0 lsb
SPV1020 detailed description doc id 17588 rev 4 13/20 ta b l e 7 shows a list of commands. each command addresses a memory location of a certain width and sets the direction of the related data. 5.11 spi timing diagram figure 5 shows the spi timing diagram. figure 5. spi timing diagram typical timing requirements are listed in ta b l e 8 and are based on characterization; these parameters are not tested in production. table 7. commands list code(hex) name r/w comment 00 not used reserved 01 nop no operation 02 shut shutdown 03 turn on required only after shut command 04 read current read 10-bit 05 read vin read 10-bit 06 read pwm read 9-bit 07 read status read read ovc (4-bit) ovv - ovt and cr 7-bit 3#,+ 8#3 -)3/ -/3) 4 l ead 4 pw 4 ds 4 dh 4 l ag 4 td 4 dv 4 ho " it " it " it " it " it " it 4 sc l k
detailed description SPV1020 14/20 doc id 17588 rev 4 table 8. typical timing requirements @ 25 c, v dd =3.3 v parameter description min. max. units fsclk sclk frequency 6 mhz tsck sclk period 167 ns tpw sclk pulse width 80 ns tlead ss lead time 80 ns tlag ss lag time 80 ns ttd sequential transfer delay 80 ns tds mosi data setup time 8 ns tdh mosi data hold time 8 ns tdv miso data valid time 20 ns tho miso data hold time 8 ns
SPV1020 typical curves doc id 17588 rev 4 15/20 6 typical curves figure 6. efficiency and power loss vs. input voltage figure 7. efficiency vs. output current ?x9 ?x?9 ? x9 ? x?9 ?? x9 ?? x?9 ? ? e ? ? ? ? ?? ? ?? ((]]v? ?9? w}?>}???t? s}o?p/v???s? s}?a ?es /}?a? ((]]v? w}?o}?? ?x9 ? x9 ?? x9 ?? x9 ?e x9 ?? x9 ? x9 ? x9 ?? x9 ?? x9 ??e? ((]]v? ?9? >}??v??? s]va?s s]va?es s]va?s s}?a ?es figure 8. quiescent current vs. output voltage figure 9. quiescent current vs. temperature ? e ? ? e ? ? ?? ?e ? ?? ? ?? ?e ? ?? e y]?v???v??u? k???s}o?p?s? dare da da?? da?? da? da?? da? wa?t ? e ? ? e re r?? r ? ? ?? ? ? ? ?? y]?v???v??u? du?????? s}?aes s}?a?s s}?a??s s}?a??s s}?a?es s}?a?s s}?a?s w a?t
typical curves SPV1020 16/20 doc id 17588 rev 4 figure 10. power efficiency mesured on the board steval-isv009v1 at t a =25 c x? x? x?? x?? x?e x?? x? x? x?? x?? xe x x? x? xe x w}?lw]v?9? /}??? wa?e?t? wa??t? wa??t? wa??t? wa??t? wa??t? wa?t? wa??t?
SPV1020 package mechanical data doc id 17588 rev 4 17/20 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 9. powersso-36 mechanical data symbol mm min. typ. max. a 2.15 2.47 a2 2.15 2.40 a1 0 0.075 b 0.18 0.36 c 0.23 0.32 d 10.10 10.50 e7.4 7.6 e0.5 e3 8.5 f2.3 g 0.075 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 m4.3 n 10deg o1.2 q0.8 s2.9 t3.65 u1.0 x 4.1 4.7 y 4.9 5.5
package mechanical data SPV1020 18/20 doc id 17588 rev 4 figure 11. powersso-36 package dimensions
SPV1020 revision history doc id 17588 rev 4 19/20 8 revision history table 10. document revision history date revision changes 07-jun-2010 1 initial release 15-nov-2010 2 updated coverpage, figure 1 , ta b l e 5 and chapter 5 16-jan-2012 3 added chapter 6 , updated figure 7 minor text changes 25-may-2012 4 ta bl e 4 . added footnote and inserted tj op min. and max. values. updated figure 3.
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